Fpga Bitstreams

Discussion in 'Technical Development' started by sprocket, Feb 24, 2016.

  1. 2017/12/15 - Decred v1.1.2 released! → Release Notes  → Downloads
  1. sprocket

    sprocket New Member

    Feb 20, 2016
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    Recently, I've seen a few posts about FPGA bistreams. I have had my ztex fpga mining decred since launch. Ultimately, I don't feel these Spartan chips will be able to compete with newer GPUs (the ztex gets 800Mh/s vs 2 to 6Gh/s for modern GPUs). I also played around and created bitstreams for smaller chips like lx45 /l x9. I realize some will say LX chips are obsolete, but I don't believe the newer xilinx chips would be cost effective; however, I'm willing to explore them.

    My interest here is around the tech, so I'd like to know if there are any other FPGA devs out there that would like to collaborate to see if we can push these chips a little further. I'm not interested in designing an fpga for anyone, but rather sharing knowledge with other FPGA devs to learn from each other and pushing these chips to their limits.

    If there is no interest, I'll probably just turn over the bitstreams to the DCR devs...but then we would never get to see what these chips could do :)
     
  2. Wolf

    Wolf Jr. Member

    Jan 25, 2016
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    I've got ideas on making kramble's better - will use more slices and clocks, but you should be able to get fuck high clock speeds.
     
  3. sprocket

    sprocket New Member

    Feb 20, 2016
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    I didn't use Kramble's code (I did try it to see if it would work for Decred but I couldnt get it to route when upgraded to 14 rounds). I ended up writing my own which uses a different approach than he did.
     
  4. Wolf

    Wolf Jr. Member

    Jan 25, 2016
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    I wrote my own for LX9, turns out it's similar to his approach, I found out later, but it's only my first draft. I have an idea for the smaller chips - right now the LX9 barely passes timing, this should fix that.
     
  5. majsta

    majsta New Member

    Feb 25, 2016
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    From my side I have tried to run kramble blake core on Altera Cyclone III with 40KLE with some idea to modify it for dcr. Point is that result was so poor that there is no worth to mention it at all. At 70MHz temperature was 90degrees and after 10 minutes FPGA was dead. Mining was not possible on stratum so only getwork pool or solo and that was good option if we consider dcr. Compilation took about 13K LE for 3 cores and I could add more of them but real problem was huge temperature rise so I don't think that Altera is suitable for this job. I could really smell that at some point balls under FPGA started to melt :) Problem with existing cores for me is that they are done in verilog and first I ll need to translate it to VHDL before any kind of optimizations.If I start doing it now, I ll do it at exact point where FPGA won't be usable for this algo at all because diff rise. Anyway, in this constant battle with FPGA usage in last 3 years I was always too late.
     
  6. Wolf

    Wolf Jr. Member

    Jan 25, 2016
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    We'll see about that on my Cyclone V. I'm writing my own from scratch in Verilog.
     
  7. majsta

    majsta New Member

    Feb 25, 2016
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    Cyclone V could be better at least regarding temperature but still I wouldn't expect much. I m excited to see some results. On the other hand Aria or even Stratix could gave more but then we are in the story how expensive those FPGA are and potential profit. If complete goal is just to prove point or if someone already have board with such chips then it makes sense.
     
  8. Wolf

    Wolf Jr. Member

    Jan 25, 2016
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    It's got 110K LEs, should be good, I think. Working on it.
     
  9. sprocket

    sprocket New Member

    Feb 20, 2016
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    I don't plan on posting my ztex code; however, below is a link to my Xilinx Spartan6 LX9 code. Of course its useless because it only runs at 4Mh/s; however, it may help inspire people to look for innovative ways to speed up the bigger boards which is the feedback I'm after :)

    https://github.com/sprocket-fpga/Decred_LX9

    Anyway, I think we all agree that the expensive big boards will do great. My hope was to see if we could get the obsolete fpga running a bit longer.
     
  10. Wolf

    Wolf Jr. Member

    Jan 25, 2016
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    Mine is currently slower, but I have an idea you didn't do - will take more clock ticks, however. I seem to not be able to pipeline for shit, though.

    EDIT: Is your midstate hardcoded?
     
  11. majsta

    majsta New Member

    Feb 25, 2016
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    Nice, what could be interesting here to add is virtual wire like in kramble miner so complete thing could be used just over JTAG and with midstate on windows.
     
  12. Wolf

    Wolf Jr. Member

    Jan 25, 2016
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    Mine uses USB serial to read in the midstate and message - if his are hardcoded, no wonder it's so fast, the synthesizer can have a field day with optimizations.
     
  13. sprocket

    sprocket New Member

    Feb 20, 2016
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    I use cgminer as the miner. It calculates the midstate and passes that along with bytes 128-139 of the Block Header to the FPGA. There is no need to pass the remaining Block Header bytes as they aren't used for anything yet.
     
  14. Wolf

    Wolf Jr. Member

    Jan 25, 2016
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    There is if you mine at a pool, because it uses 12b of extranonce. Well, the "stratum" implementation does.
     
  15. sprocket

    sprocket New Member

    Feb 20, 2016
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    My ztex code has those bytes included. The LX9 was just for fun when I saw you tried it out. I don't intend on using it to mine anything, I just wanted to share it as a POC.

    Also, regarding your earlier comment about using more clock ticks, that's not an issue unless you slow down throughput. With the ztex code I played around with anywhere from 1 clock tick per round up to 16 ticks...but I kept my throughput the same...one hash was done each clock. What I found was there was a balance...more ticks may be faster, but uses more area. And as you know it's a balancing act getting these things to implement.
     
  16. Wolf

    Wolf Jr. Member

    Jan 25, 2016
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    I know, I'm working on it, but as I said, I'm sucking at pipelines atm. Also, I doubled my hashrate from the original, stupid mistake I made wasting a clock tick.
     
  17. PaulieGoto

    PaulieGoto New Member

    Feb 25, 2016
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    #17 PaulieGoto, Feb 26, 2016
    Last edited: Mar 1, 2016
    As per my experience Cyclone V could be better at least regarding temperature but still I wouldn't expect much.
    On the other hand Aria or even Stratix could gave more but then we are in the story how expensive those FPGA are and potential profit.
    If complete goal is just to prove point or if someone already have board with such chips then it makes sense.

    hdi pcb
     
  18. Wolf

    Wolf Jr. Member

    Jan 25, 2016
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    Already around 50MH/s with a Cyclone V, and I've room bump the clock a little. Using under 40% of the logic.
     
  19. coindozer

    coindozer New Member

    Jan 20, 2016
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    I just started to learn verilog inorde to mine some coins with my fpga but i didn't get far .. started to work from the Kramble code but still somewhere lost with the midstate code. Also it's kind of hard to find any information on how it should be working in a high level overview.
    Thanks sprocket I'm going to take a look at your code. Also need to find out how to link the cgminer with the fpga...
    Looking forward to Wolf's code (I also have an altera FPGA)
     
  20. Wolf

    Wolf Jr. Member

    Jan 25, 2016
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    I have two implementations for larger chips (larger being relative, I mean not as horrid as the LX9) - one I can get 100MH/s easy on my Cyclone V, the other I think can do better, but is being butchered by the synthesizer, and I need to play with the settings some more.
     

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