So I did. It successfully hashes, incrementing a nonce (starting from zero) until it reaches a hash below a target (which is currently fixed in the design) and returns the 32-bit nonce that resulted in the hash below the target. I optimized as best I could for speed given the brutal constraints on the LX9. I kept the stock clock of 50Mhz, but only just - without setting ISE to optimize for timing performance, it won't meet the timing constraints. I've been playing with the design, cleaning it up and such, but it usually occupies around the high 80% to low 90% of slices on the LX9. I don't have solid hashrate numbers as of yet for two reasons: One, diff1 is a little high for it, and would take a while to find one share, and two, I have some sort of I/O related bug. It accepts work sometimes, but other times returns an invalid nonce. I used a test program which runs Blake-256 14 round on the CPU to verify the results - they're usually right, but there's still something wrong in my I/O design. Anyways, point made - you CAN fit it on super small, cheap FPGAs. EDIT: FIXED! Now, only one issue with gauging hashrate - any timer I use would either have to include the time spent passing the data over USB serial and getting the nonce back over the same, or exclude it and run the risk of estimating a little high. EDIT2: I tried benchmarking with and without the actual send over USB serial counted, and it seems to have an extremely small, if any, effect. Hashrate seems to be 0.82MH/s - 0.85MH/s. Power use is as yet unknown - it's powered over USB. EDIT3: Oops. Apparently, I was mining at diff1 for Decred this whole time. I thought the target was 0x00000000 - but it's 0x000000FF.